Home // SIMUL 2013, The Fifth International Conference on Advances in System Simulation // View article

ComCas: A Compiled Cycle Accurate Simulation for Hardware Architecture

Authors:
Adrien Bullich
Mikaël Briday
Jean-Luc Béchennec
Yvon Trinquet

Keywords: Cycle Accurate Simulation; interpreted simulation; compiled simulation; HADL

Abstract:
This article is in the context of real-time embedded systems domain. These critical systems require an important effort in validation and verification that can be done at many abstraction levels, from high-level application model to the actual binary code using an accurate model of the processor. As the development of a handwritten simulator of a processor at a cycle accurate level is a difficult and tedious work, we use Harmless, a hardware description language that can generate both a functional and a cycle accurate simulators. The latter gives a temporal information of the simulation execution, but at the cost of a heavy computation overhead. This paper applies the compiled simulation principles to a cycle accurate simulator. It shows that this simulation mechanism can reduce computation time up to 45%, preserving timing information.

Pages: 137 to 142

Copyright: Copyright (c) IARIA, 2013

Publication date: October 27, 2013

Published in: conference

ISSN: 2308-4537

ISBN: 978-1-61208-308-7

Location: Venice, Italy

Dates: from October 27, 2013 to October 31, 2013