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Ultra Low Power CMOS Phase Locked Loop synthesizer for Very High Frequencies

Authors:
Nayera Ahmed
Akram Malak

Keywords: PLL; CMOS; ,frequency; synthesizer

Abstract:
This paper describes the design of an essential component in wireless transceivers, the frequency synthesizer. The synthesizer is implemented using Phase Locked Loop(PLL). Second order PLL, type II, with a reference frequency 10MHz is designed using 180nm analog CMOS process technology. The synthesizer generates signals in frequency range of 10-100 MHz. The simulated power consumption of the system is 37μW with a deviation from the true periodicity; root mean square periodic jitter is in range of 5 ps.

Pages: 10 to 13

Copyright: Copyright (c) IARIA, 2014

Publication date: February 23, 2014

Published in: conference

ISSN: 2308-4480

ISBN: 978-1-61208-317-9

Location: Nice, France

Dates: from February 23, 2014 to February 27, 2014