Home // International Journal On Advances in Systems and Measurements, volume 11, numbers 1 and 2, 2018 // View article

Low Power Optimized and DPA Resistant D-FF for Versatile Mobile Applications

Authors:
Karol Niewiadomski
Dietmar Tutsch

Keywords: FPGA; D-FF; charge recycling; low-power; differential power analysis

Abstract:
Starting from early, simple logic gates, the development of integrated electronics made impressive proceedings in terms of performance and complexity. These chips can be found everywhere in daily life, serving the purpose of processing tasks, which are mostly too complicated, dangerous or tiring to human's nature. Whilst the use of integrated circuits was limited to classic applications, e.g., personal computers, servers, mainframes, etc., the application scope was continuously enlarged over the years. Hence, microprocessors began to add more and more computational power to various mobile devices, e.g., cell phones, tablets and even vehicles. Nowadays, smartphones provide more processing resources than bulky mainframes used for ballistic calculations ever did. It is thinkable that smartphones and tablets will replace the classic personal computers in many households, due to the mobility, versatility and simplicity they offer. Another example for fast digitalization are vehicles. Next generation cars will offer a growing number of automated driving assistance systems, which shall add safety and comfort to daily traffic situations. Further steps towards vehicle to vehicle and vehicle to infrastructure communications will produce tremendous amounts of data. As a consequence, more processing capabilities will be needed over time and therefore challenging the lifetime of batteries. Architectural improvements towards battery lifetime extension are an inevitable step, however, power sensitive adaptions must be done at a deeper hierarchical level. Since each data processing logic heavily depends on registers implemented by data flip-flops, this paper presents a newly designed charge recycling data flip-flop. Major focus during research and development was put on low power design aspects as well as on security-related enhancements to counter differential power analysis. This new design is compared to a selection of various, already existing implementations.

Pages: 100 to 110

Copyright: Copyright (c) to authors, 2018. Used with permission.

Publication date: June 30, 2018

Published in: journal

ISSN: 1942-261x