Home // International Journal On Advances in Systems and Measurements, volume 13, numbers 1 and 2, 2020 // View article

Fast FPGA-Placement Using a Gradient Descent Based Algorithm

Authors:
Timm Bostelmann
Tobias Thiemann
Sergei Sawitzki

Keywords: EDA; FPGA; placement; gradient descent

Abstract:
Programmable circuits and, nowadays, especially Field-Pro-grammable Gate Arrays (FPGAs) are widely applied in computationally demanding signal processing applications. Considering modern, agile hardware/software codesign approaches, an Electronic Design Automation (EDA) process not only needs to deliver high quality results, but also has to be swift because software compilation is already distinctly faster. Slow EDA tools can in fact act as a kind of show-stopper for an agile development process. One of the major problems in EDA is the placement of the technology-mapped netlist to the target architecture. In this work, a method to reduce the runtime of the netlist placement for FPGAs is evaluated. The approach is a variation of analytical placement, with the distinction that a gradient descent is used for the optimization of the placement. This work is an extended version of a previous publication of the authors on this topic. Additionally, it is based on previous publications of the authors, in which a placement algorithm using self-organizing maps is introduced and optimized. In comparison, the gradient placement approach is shown to be up to 3.8 times faster than the simulated annealing based reference. The quality regarding the critical path is shown to be about 43 percent worse on average. The bounding-box and routing-resource costs are shown to be about equal to the reference.

Pages: 175 to 184

Copyright: Copyright (c) to authors, 2020. Used with permission.

Publication date: June 30, 2020

Published in: journal

ISSN: 1942-261x