Home // International Journal On Advances in Systems and Measurements, volume 2, number 1, 2009 // View article

System-on-Chip Implementation of Neural Network Training on FPGA

Authors:
Ramón J. Aliaga
Rafael Gadea
Ricardo J. Colom
José M. Monzó,
Christoph W. Lerche
Jorge D. Martínez

Keywords: artificial neural networks (ANN), backpropagation, field-programmable gate array (FPGA), multilayer perceptron (MLP), system-on-chip (SoC).

Abstract:
Implementations of Artificial Neural Networks (ANNs) and their training often have to deal with a trade-off between efficiency and flexibility. Pure software solutions on general-purpose processors tend to be slow because they do not take advantage of the inherent parallelism, whereas hardware realizations usually rely on optimizations that reduce the range of applicable network topologies, or attempt to increase processing efficiency by means of low-precision data representation. This paper describes a mixed approach to ANN training, based on a system-on-chip architecture on a reconfigurable device, where a coprocessor with a large number of parallel neural processing units is controlled by software running on an embedded processor. Software control and the use of floating-point arithmetic guarantee system generality, and replication of processing logic is used to exploit parallelism. Implementation of the proposed architecture on a low-cost Altera FPGA achieves a performance of 431 MCUPS (millions of connection updates per second).

Pages: 44 to 55

Copyright: Copyright (c) to authors, 2009. Used with permission.

Publication date: June 7, 2009

Published in: journal

ISSN: 1942-261x