Home // International Journal On Advances in Systems and Measurements, volume 3, numbers 1 and 2, 2010 // View article

The Two-dimensional Superscalar GAP Processor Architecture

Authors:
Sascha Uhrig
Basher Shehan
Ralf Jahr
Theo Ungerer

Keywords: High Performance Processors, Reconfigurable Architecture, Instruction Level Parallelism

Abstract:
In this paper we evaluate the new Grid Alu Processor architecture that is optimized for the execution of sequential instruction streams. The Grid Alu Processor architecture comprises an in-order superscalar pipeline front-end enhanced by a configuration unit able to dynamically issue dependent and independent standard machine instructions simultaneously to the functional units, which are organized in a two dimensional array. In contrast to well-known coarse-grained reconfigurable architectures no special synthesis tools are required and no configuration overhead occurs. Simulations of the Grid Alu Processor showed a maximum speedup of 2.56 measured in instructions per cycle compared to the results of a comparable configured SimpleScalar processor simulator. Further improvements introduced in this paper lead to a top speedup of about 4.65 for one benchmark. Our evaluations show that with restricted hardware resources, the performance is only slightly reduced. The gain of the proposed processor architecture is obtained by the asynchronous execution of most instructions, the possibility to issue multiple depending instructions at the same cycle and the acceleration of loops.

Pages: 71 to 81

Copyright: Copyright (c) to authors, 2010. Used with permission.

Publication date: September 5, 2010

Published in: journal

ISSN: 1942-261x