Home // International Journal On Advances in Systems and Measurements, volume 6, numbers 1 and 2, 2013 // View article

LUT Saving in Embedded FPGAs for Cache Locking in Real-Time Systems

Authors:
Antonio Martí Campoy
Francisco Rodríguez-Ballester
Rafael Ors Carot

Keywords: Real-Time Systems; Cache Locking; FPGA; Memory Hierarchy

Abstract:
In recent years, cache locking have appeared as a solution to ease the schedulability analysis of real-time systems using cache memories maintaining, at the same time, similar performance improvements than regular cache memories. New devices for the embedded market couple a processor and a programmable logic device designed to enhance system flexibility and increase the possibilities of customisation in the field. This arrangement may help to improve the use of cache locking in real-time systems. This work proposes the use of this embedded programmable logic device to implement a logic function that provides the cache controller the information it needs in order to determine if a referenced main memory block has to be loaded and locked into the cache; we have called this circuit a Locking State Generator. Experiments show the requirements in terms of number of hardware resources and a way to reduce them and the circuit complexity. This reduction ranges from 50% up to 80% of the number of hardware resources originally needed to build the Locking State Generator circuit.

Pages: 190 to 199

Copyright: Copyright (c) to authors, 2013. Used with permission.

Publication date: June 30, 2013

Published in: journal

ISSN: 1942-261x