Home // International Journal On Advances in Systems and Measurements, volume 8, numbers 1 and 2, 2015 // View article
Authors:
Abdul Wahab Majeed
Halfdan Solberg Bechmann
Yngvar Berg
Keywords: ULV; Carry Gate; NP domino
Abstract:
abstract: This paper is based on two parts. In Part 1, we shall present a new Ultra Low Voltage Static differential NOR topology. This will show how Ultra Low Voltage circuits are designed and what are the pros and cons of these circuits. In Part 2, utilizing the design presented in Part 1, we shall present a novel design of an Ultra Low voltage Carry Gate. This shall emphasize the use of such design in an application such as carry gate. The Ultra Low Voltage topologies presented in Part 1 are well known for their high speed relative to conventional CMOS topologies regarding subthreshold operation. The main objective is to target the robustness of the presented ciruits. We shall also imply as to what extent these circuits can be improved and what their benefits, compared to conventional topologies, are. The design presented in Part 2, compared to a conventional CMOS carry gate, is area efficient and high speed. The relative delay of a Ultra Low Voltage carry gate lies at less than 3% compared to conventional CMOS carry gate. The circuits are simulated using the TSMC 90nm process technology and all transistors are of the Low Threshold Voltage type.
Pages: 113 to 123
Copyright: Copyright (c) to authors, 2015. Used with permission.
Publication date: June 30, 2015
Published in: journal
ISSN: 1942-261x