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Optical Link Testing and Parameters Tuning with a Test System Fully Integrated into FPGA

Authors:
Anton Kuzmin
Dietmar Fey

Keywords: Optical fiber communication; Transceivers; FPGA; Microcontrollers; Embedded software

Abstract:
Development, characterization and performance op- timization of systems utilizing FPGAs with high-speed serial transceivers to implement optical links with 1 to 10 Gbps data rate is a complex task and it poses several challenges for design engineers. In this paper, an effective approach is presented designed to address these challenges based on the use of diagnostic features implemented in the transceivers and a soft-IP microcontroller system instantiated in the FPGA. The use of the soft-IP controller allows a single-point access to the control and diagnostic interfaces of all components forming the link. Combined with computational capabilities and a high-level programming language interpreter running on the soft-IP CPU inside the FPGA, it enables extensive optical link performance evaluation without relying on any additional test and mea- surement equipment and significantly shortens debugging and testing times. The implementation demonstrates the feasibility and effectiveness of the proposed approach to utilization of on- chip diagnostic capabilities.

Pages: 121 to 126

Copyright: Copyright (c) IARIA, 2012

Publication date: November 18, 2012

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-233-2

Location: Lisbon, Portugal

Dates: from November 18, 2012 to November 23, 2012