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Performance Impact of Correctable Errors on High Speed Buses

Authors:
Daniel Ballegeer
David Blankenbeckler
Subhasish Chakraborty
Tal Israeli

Keywords: high speed bus;interconnect;bus errors;performance;BER;I/O;bus

Abstract:
Modern high speed serial buses are generally required by specification to achieve a maximum bit error ratio. Are these requirements too restrictive? This paper will look at a series of studies on Peripheral Component Interconnect Express and Serial AT Attachment, investigating the impact of bit error ratio on bus performance. The results of these studies suggest that typical bit error ratio requirements may be conservative. The findings suggest that alternative bus performance specifications should be considered that would open new possibilities for design, validation and manufacturing test tradeoffs.

Pages: 54 to 59

Copyright: Copyright (c) IARIA, 2014

Publication date: October 12, 2014

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-370-4

Location: Nice, France

Dates: from October 12, 2014 to October 16, 2014