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An Experimental Comparative Study of Fault-Tolerant Architectures

Authors:
Imran Wali
Arnaud Virazel
Alberto Bosio
Patrick Girard

Keywords: fault tolerant architecture; fault tolerance capability assessment

Abstract:
This paper provides a comparative study based on experiments performed on four similar fault-tolerant architectures intended to reduce errors caused due to faults in combinational logic parts of microelectronic circuits and systems. The compared merits include area, power, performance and fault tolerance capability. The experimental results show that the improved Hybrid Fault-Tolerant Architecture can handle transient faults as effectively as Partial-TMR and exhibits permanent fault tolerance capability similar to that of Full-TMR. It offers 11.8% and 20.5% power saving compared to Partial and Full-TMR respectively. Furthermore, it can handle the fault accumulation effect better than TMR, hence an ideal candidate for low-power long duration mission-critical applications.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2015

Publication date: November 15, 2015

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-441-1

Location: Barcelona, Spain

Dates: from November 15, 2015 to November 20, 2015