Home // VALID 2017, The Ninth International Conference on Advances in System Testing and Validation Lifecycle // View article


A Method to Determine the Static NBTI Stress Time of an Embedded Component in an Integrated Circuit

Authors:
Puneet Ramesh Savanur
Spyros Tragoudas

Keywords: Negative bias temperature instability (NBTI); counterfeit; aging; odometer; built-in self-test (BIST)

Abstract:
This paper presents a simple mechanism to accurately estimate the number of clock cycles that an integrated circuit (IC) has operated. It is achieved by measuring the delay of an embedded component due to static negative bias temperature instability (NBTI) effects. Simulations with the HSPICE tool, using 45nm predictive technology model and a NBTI degradation model are presented. The results also indicate that using static NBTI aging model aides in very early stress time detection.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2017

Publication date: October 8, 2017

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-593-7

Location: Athens, Greece

Dates: from October 8, 2017 to October 12, 2017