Declaraciones Locales

entity FULLADD is

port (A,B,CIN : in bit;

SUM, CARRY : out bit);

end FULLADD;

architecture STRUCT of FULLADD is

signal I1, I2, I3 : bit;

component HALFADD

port(A,B : in bit;

SUM, CARRY : out bit);

end component;

component ORGATE

port(A,B : in bit;

Z : out bit);

end component;

begin

u1:HALFADD port map (A,B,I1,I2);

u2:HALFADD port map (I1,CIN,SUM,I3);

u3:ORGATE port map (I3,I2,CARRY);

end STRUCT;