El Bucle “for”

entity EX is

port (A : in std_logic_vector(0 to 15);

SEL : in integer range 0 to 15;

Z : out std_logic);

end EX;

architecture RTL of EX is

begin

WHAT: process (A, SEL)

begin

for I in 0 to 15 loop

if SEL = I then

Z <= A(I);

end if;

end loop;

end process WHAT;

end RTL;