Codificación de los Estados
architecture RTL of FSM is
type ESTADO is (IDLE, RW_CYCLE, INT_CYCLE, DMA_CYCLE);
signal ESTADO_ACTUAL, ESTADO_SIGUIENTE : ESTADO;
architecture RTL of FSM is
constant IDLE:std_logic_vector(1 downto 0):=00;
constant RW_CYCLE:std_logic_vector(1 downto 0):=01;
constant INT_CYCLE:std_logic_vector(1 downto 0):=10;
constant DMA_CYCLE:std_logic_vector(1 downto 0):=11;
signal ESTADO_ACTUAL, ESTADO_SIGUIENTE: std_logic_vector(1 downto 0);