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Comparison of off-chip interconnect validation to field failures

Authors:
Michael Shepherd
David Blankenbeckler
Adam Norman

Keywords: DDR, DRAM, memory, bus margin

Abstract:
Memory subsystem errors continue to be a common problem in modern computer systems. Through a large scale field study, this paper will introduce the interconnect transient margin validation metrics and compare to the observed field failures. The results will demonstrate that transient bus errors are not a dominant cause of system memory problems.

Pages: 121 to 125

Copyright: Copyright (c) IARIA, 2011

Publication date: October 23, 2011

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-168-7

Location: Barcelona, Spain

Dates: from October 23, 2011 to October 29, 2011