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System Debug and Validation: Use case Based Perspective

Authors:
Bhushan Naware
Arun Pai
Ravinder Singh

Keywords: Test Plan; Use case; Scenario; Win-DBG; JTAG; Silicon Debug

Abstract:
Concept and Design of systems with sheer complexity at various abstraction levels is becoming tedious and time consuming process. To comply with the expected requirements, subsequent validation and verification becomes even more time consuming and expensive. When it comes to platform level validation and debug, there are various fronts that are to be looked at with great depth. In case of laptops/desktops the system stack includes hardware, silicon, firmware, bios, operating system, various drivers and applications. In complex systems, finding root cause of issues caught at platform validation is challenging and increases debug throughput. In this paper, we will introduce a methodology for validation and debug that could be applied across similar systems. This methodology is bound to shorten the life span of test plan creation, early identification, debug and root cause of issues. This will result in cost saving and shorter time to market.

Pages: 1 to 6

Copyright: Copyright (c) IARIA, 2018

Publication date: October 14, 2018

Published in: conference

ISSN: 2308-4316

ISBN: 978-1-61208-671-2

Location: Nice, France

Dates: from October 14, 2018 to October 18, 2018