Descripción VHDL

library IEEE;

use IEEE.Std_Logic_1164.all;

use IEEE.Std_Logic_arith.all;

use IEEE.Std_Logic_signed.all;

entity CONTADOR is

port ( CLK : in std_logic;

PRESET : in std_logic;

OUT_DATA : out std_logic_vector (0 to 7) );

end CONTADOR;

architecture RTL of CONTADOR is

...