Descripción VHDL

architecture RTL of CONTADOR is

signal cnt : std_logic_vector (0 to 7);

begin

process (CLK)

begin

if (CLK'event and CLK='1') then

if (PRESET = '0') then

cnt <= "11111111";

else

cnt <= cnt - 1;

end if;

end process;

OUT_DATA <= cnt;

end RTL;